Senior Design Verification Engineer

Tasks
Develop verification and test plans, develop test benches, develop simulation environments, write behavioral models and checkers, write directed tests, analyze test coverage, and formal verification.

Experience
Complex system verification including processor, memory, I/O bus, network and storage sub-systems. Have written parsers, compilers, and/or test case generators. Simulation experience also desired. Skills and Tools: Verilog/PLI, C/C++, Perl, Synopsys, VCS, Formality, PLI, FLEX, Bison, RTPG.

Requirements
BS (MS preferred) Electrical or Computer Engineering; 8+ years experience.

  

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