Tasks
Develop floor planning, auto place and route (APR) and chip integration for InfiniBand target, host, and switch products. Verify standard cell library elements, compiled memories, and I/O cells for use with the physical design flows. Route design including clock trees and power grids. Perform parasitic extraction and static timing analysis. Perform in-place optimizations to resolve timing issues. Develop a single-pass timing driven methodology using 3rd party tools from synthesis, APR, 3D extraction, and delay calculation. Develop reliability verification and analysis technology.

Requirements
Bachelor's degree in related discipline (or equivalent experience) plus 4-6 years' experience in floor planning, placement, routing, extraction, optimization, and physical verification of high-speed digital integrated circuits using Cadence and Avant! tools (Apollo, Planet-PL, Solar, Silicon Ensemble, Dracula, etc.). Must possess detailed experience in static timing and APR and a good understanding of synthesis. Must also have programming skills in C++, Perl, Tcl or equivalent language.

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