Tasks
Responsible for the coordination of backend verification and developing verification flows. Perform chip level backend physical verification. Create and maintain technology files, applications, and standards for physical design and verification. Maintain LVS/DRC/LPE functions. Do Perl, shell script writing. Must have in-depth knowledge of backend tools and flows; hands-on experience with Avanti Hercules and Avanti Apollo; and accurate parasitic extraction skills. Experience in power, process, noise or other specialty a plus.

Requirements
BSEE plus minimum of 5 years' experience in physical / layout verification. Successful track record of delivering products to production and prior experience in timing closure, parasitic extraction, clock/power distribution and analysis, and tapeout issues is a must. Circuit level comprehension of time critical paths. SPICE and/or HSPICE experience a plus.

When submitting your resume, please include position(s) of interest and Word formatted (or ASCII text) file.