Tasks
Develop synthesis scripts, generate wire load models, design clock trees, perform logic synthesis, estimate power consumption, work with physical designers to: define chip floor plan, place & route, parasitic extraction, static timing analysis.

Requirements
BS or MS Electrical Engineering plus 3-5 years experience in integration for sub-micron, >500 K gates, >0.5 M bit, >125 MHz, multiple clock domains, ASIC or COT designs. Skills and Tools: Synopsys, PrimeTime, ATPG, VCS, Formality, Perl, Cadence, Avanti.

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