Tasks
Perform circuit design and timing analysis of high-speed, mixed-signal (i.e. both analog and digital) circuits in deep sub-micron CMOS technologies, in particular serializer/deserializer blocks and low voltage, differential output buffers at 2.5 Gb/s and beyond. Conduct transistor-level circuit simulations with chip, package, and system-level parasitics included if necessary to ensure that the performance of the circuits meet specifications. Direct layout designers on the physical layout of the circuits to optimize performance. Verify, debug and characterize the performance of the circuits in the lab. Work with test engineers to develop test programs for production testing of the circuits.

Requirements
BS or MS Electrical Engineering plus 7+ years' experience with circuit design and timing analysis of high-speed (>1Gb/s preferrable) digital or analog cirucits. Previous design experience in PLLs (Phase-Loced Loops), clock generators, frequency synthesizers, clock/data recovery circuits, high-speed transceivers, line drivers or CML (Current-Mode Logic) circuits desirable.

Tools
SPICE, PrimeTime, parasitic extraction.

When submitting your resume, please include position(s) of interest and Word formatted (or ASCII text) file.